New Memory Organizations for 3D DRAM and PCMs

3D DRAM and PCMs in Processor Memory Hierarchy

In this paper we describe and evaluate two possible architectures using 3D DRAMs and PCMs in the processor memory hierarchy. We explore using (a) 3D DRAM as main memory with PCM as backing store and (b) 3D DRAM as the Last Level Cache and PCM as the main memory. In each of these configurations, since the proposed main memories are significantly faster than today’s off-chip 2D DRAMs for main mem...

Memory organizations for 3D-DRAMs and PCMs in processor memory hierarchy

A Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost

3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern systems, by leveraging through silicon vias (TSVs) to deliver higher external memory channel bandwidth. Today’s systems, however, cannot fully utilize the higher bandwidth offered by TSVs, due to the limited internal bandwidth within each layer of the 3D-stacked DRAM. We identify that the bottleneck to enab...

Re-Architecting DRAM Memory Systems with 3D Integration and Photonic Interfaces

In recent years, due to well-known “memory-wall” limitations, DRAM latency and energy/bit characteristics have not improved as rapidly as DRAM capacity and bandwidth with technology scaling. Despite plenty of research efforts during the last decade to overcome the hurdles in DRAM scaling, high performance computing systems of the future will still require improvements in DRAM latency and bandwi...

A Study of Page Placement and Migration in Heterogeneous Flat-Addressable Memories

The volume of data generated by research, commercial, industrial, communication, entertainment and other fields is growing exponentially. There is a need for faster and very large amounts of main memory for analyzing such volumes of data in reasonable amounts of time. In addition, these systems need to be as energy efficient as possible, since the energy requirements of most high-performance co...